Many computational and networking problems require hierarchical storage and very fast access to terabyte-size data sets. Servers typically use large dynamic random-access memory banks for high performance storage (i.e. in-memory databases) and arrays of solid state or rotating disk drives connected over a serial disk interface for high capacity storage. These disk interfaces are either directly integrated into System-on-Chip (SoC) central processing units (CPUs), or are provided by a peripheral disk interface chip connected to the CPU's input/output (I/O) expansion bus.
In multi-socket servers, if one CPU needs to access data stored in the I/O subsystem of another CPU socket, the other CPU cooperates by launching the request, and the data is transferred between CPU sockets over a cache coherency interface. In the case of Intel Xeon™ class CPUs, this coherency interface is the QuickPath Interface (QPI™), which is a wide, fast, very low latency inter-chip bus. Other types of multi-socket CPUs use different coherency interface specifications with similar functions.
Large DRAM arrays are expensive, volatile, and require large physical volume and operational power. Individual disk drives, on the other hand, have specific read and write bandwidth limitations. Multiple drives need to be used in parallel to achieve high disk channel bandwidth. The single lane serial I/O interfaces that connect the drives to the disk controller in typical servers have a maximum sustained bandwidth of a few gigabits per second. Furthermore, the need to get multiple CPU chips involved in a simple disk transaction in multi-socket servers adds overhead.